1. Field of the Invention
The present invention relates to an output circuit, and more particularly to an output circuit for a memory circuit having a binary signal as an input.
2. Description of the Prior Art
In the semiconductor devices, there is known a type, such as the so-called bytewide, which has a plurality (sixteen, for example) of input and output (I/O) terminals, wherein an I/O circuit is provided for each of these plurality of I/O terminals. Referring to FIG. 1, a conventional output circuit will be described. In FIG. 1, only a specific circuit configuration of the output circuit is illustrated, omitting the description about the input circuit. An output circuit is constituted by connecting in series N-channel transistors Tr1 and Tr2 between a power terminal Vcc and a ground terminal Vss. A signal supplied to a first terminal OUT-A is applied to the gate of the transistor Tr1 via an inverter 11 and a bootstrap circuit 13, and a signal supplied to a second terminal OUT-B is applied to the gate of the transistor Tr2 via an inverter 12. An N-channel transistor Tr3 is connected between the gate of the transistor Tr1 (node A) and the I/O terminal, with its gate connected to the ground terminal Vss.
A boosting signal Bt is applied to the bootstrap circuit 13 to boost the potential of the node A to a value higher than the power supply voltage Vcc. Accordingly, it is possible to boost the potential of the node A, and eventually raise the potential of the I/O terminal to a high level exceeding Vcc, by supplying the boosting signal Bt after the output of the I/O terminal raises the potential Vcc-Vth (where Vth is the threshold voltage of the transistor Tr1) through application of a low level signal and a high level signal to OUT-A and OUT-B, respectively.
Then a high level signal and a low level signal are applied to OUT-A and OUT-B, respectively, the I/O terminal goes to a low level.
To use the I/O terminal as an input terminal, the output circuit is disabled by bringing both transistors Tr1 and Tr2 to the off-state by applying high level signals to OUT-A and OUT-B. The transistor Tr3 is provided to cope with the so-called undershoot condition in which the potential of the I/O terminal in this state becomes lower than the ground potential. That is to say, if the transistor Tr3 were absent, the potential of the I/O terminal would become lower than the ground potential, and the transistor Tr1 would be turned on when the absolute value of the potential exceeds the threshold voltage of the transistor Tr1. At this time, the voltage between the source and the drain of the transistor Tr1 would be higher than Vcc. When the source-drain voltage of a MOS transistor is large, the substrate current, which is a part of the channel current, that flows in the substrate at a pinched-off region of the channels is increased markedly, rising the potential of the substrate. By installing the transistor Tr3, it becomes possible to prevent turning-on of the transistor Tr1 during undershooting by turning on the transistor Tr3 before the transistor Tr1 is turned on, and connecting the node A (which is at the low level at this time) and the I/O terminal.
A memory circuit for multibit output is provided with an output circuit, such as shown in FIG. 1 and described in the above, for every I/O terminal. Now let us consider the read operation of a memory circuit for the case when it has 16, for example, I/O terminals. When one specified I/O terminal goes to the high level and the remaining 15 I/O terminals go to the low level, the 15 output circuits provided corresponding to the 15 I/O terminals simultaneously discharge electric charges to the ground terminal Vss. As a result, there is generated a ground noise in which the ground potential goes up. Note, however, that the ground noise may also be generated due to some other reasons.
If the ground potential exceeds the threshold voltage of the transistor Tr3 shown in FIG. 1, the transistor Tr3 in one specified output circuit is turned on. Consequently, there arises a problem in that it takes a longer time to raise the potential of the node A and the operation of the system becomes slow. Moreover, if the ground noise occurs during application of the boosting signal Bt, the transistor Tr3 is turned on, preventing rise of the potential of the node A beyond Vcc+Vth, which results in a problem that a sufficiently high output level (higher than Vcc) cannot be obtained.